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SystemVerilog Assertion是针对数字电路设计和验证技术初/中级学员的课程,是数字电路设计和验证工程师必须掌握的一项ASIC/SoC设计验证技能。该课程不仅是对SystemVerilog Assertion的语法描述,更重要的是对SystemVerilog Assertion技术的理论和用法的归纳,总结和升华,通过SystemVerilog Assertion课程的学习可以快速成为一名合格的IC设计和验证工程师,构建基于SystemVerilog Assertion的RTL设计和验证平台,熟练掌握Assertion语义语法,进而为掌握IC高级设计和验证技术打下坚实的基础。
课程大纲
1、SystemVerilog Assertion Methodology
2、SystemVerilog Assertion Type
3、SystemVerilog Assertion Syntax-1
4、SystemVerilog Assertion Syntax-2
5、SystemVerilog Assertion Checker Library and AIP
6、SystemVerilog Assertion Debugging
7、SystemVerilog Assertion Pattern
8、SystemVerilog Assertion Plan
9、SystemVerilog Assertion Coverage and with VHDL
课程实验
Lab1. Assertion in interface and program
Lab2: Assertion in module and binded with RTL design
Lab3: Assertion debugging with DVE
Lab4: Assertion in testbench